Reference is made to FIG. 1 which shows a circuit diagram of a conventional current controlled oscillator (CCO) circuit 10. The CCO circuit 10 includes a ring oscillator 12 formed by an odd number of series-connected inverting delay elements 14(1) to 14(n). An output of one inverting delay element is connected to the input of a next inverting delay element, and a last one of the inverting delay elements 14(n) has its output connected to the input of a first one of the inverting delay elements 14(1). The inverting delay elements 14 are coupled between a source node 18 at a source voltage Vs level and a ground node at a ground voltage level. The level of the source voltage at node 18 is dependent on the threshold voltages of the transistors in the inverting delay elements 14 and the corresponding circuit overdrive. Each inverting delay element 14 provides an amount of delay from input to output which is dependent on a charging current Icharge that is sourced by a current source 30 from a supply voltage Vdd to the source node 18. The oscillation frequency fo of the oscillating output signal 13 (Fout) generated by the ring oscillator is dependent on the amount of delay, and thus the output frequency can be controlled by the charging current Icharge. The oscillation amplitude of the oscillating output signal 13 (Fout) is controlled by the source voltage Vs at node 18.
The magnitude of the charging current Icharge output by the current source 30 is set by a voltage control signal CONT. In an embodiment, a p-channel transistor 32 forms the current source 30, with a source of the transistor 32 connected to the supply voltage Vdd node and a drain of the transistor 32 connected to source the charging current Icharge to the source node 18. The gate of transistor 32 is coupled to receive the voltage control signal CONT. The current source 30 accordingly functions as a voltage-to-current converter circuit. The control signal CONT controls the conductivity of the transistor 32 and hence the magnitude of the charging current Icharge sourced to the source node 18 of the ring oscillator. The voltage magnitude of the control signal CONT is accordingly used to set the oscillation frequency fo of the oscillating output signal 13 Fout.
FIG. 2 shows a block diagram of a frequency synthesizer circuit 50 of a locked loop operating type such as a frequency locked loop (FFL) or phase locked loop (PLL). The circuit 50 includes a controlled oscillator 52 which, in this implementation, is a CCO circuit 10 of the type shown in FIG. 1. The oscillating output signal 13 Fout from the ring oscillator 12 of the controlled oscillator 52 is level shifted by a level shifter circuit 54 and divided by a frequency divider circuit 56 to generate an oscillating feedback signal 15 (Ffb) having a frequency fo/N where N is the divider value (integer or fraction) of the frequency divider circuit 56. Level shifting is needed in the case of the ring oscillator 12 because the oscillating output signal 13 Fout has an oscillation amplitude at the voltage Vs of the source node 18 and it is required that the oscillating feedback signal 15 Ffb instead have an amplitude at the supply voltage Vdd level of the locked loop circuit 50. A phase-frequency detector circuit 60 compares the phase and frequency fo/N of the oscillating feedback signal 15 Ffb to the phase and frequency fr of an oscillating reference signal 17 Fref to generate an error signal ERR indicative of the determined difference in phase-frequency. The error signal ERR is fed to a charge pump (CP) 62 that outputs an equivalent error voltage Verr that is filtered by a filter circuit 64 (for example, of the low pass filter type) to generate the voltage control signal CONT. The control signal CONT, as discussed above in connection with FIG. 1, is applied to the voltage-to-current converter 66 formed by the current source 30 to generate the charging current Icharge which controls the frequency fo of the oscillating output signal 13 Fout. The feedback loop of the frequency synthesizer circuit 50 functions to control the magnitude of the control signal CONT so that the phase and frequency fo/N of the oscillating feedback signal 15 Ffb, which is derived from the oscillating output signal Fout from the ring oscillator 12, is driven to equal the phase and frequency fr of the oscillating reference signal 17 Fref.
In some implementations, circuitry of the frequency synthesizer circuit 50 may be referenced to two different power supply domains. This is shown in FIG. 3. A first power domain has a positive voltage at the Vdda level (primarily used as the supply for analog circuit blocks, and is thus referred to as the analog supply of the locked loop circuit) and a second power domain has a positive voltage at the Vddb level (primarily used as the supply for digital circuit blocks, and is thus referred to as the digital supply of the locked loop circuit). In a typical implementation, Vddb is less than Vdda, but it will be understood that this is just an example. The phase-frequency detector circuit 60, charge pump 62, filter circuit 64 and voltage-to-current converter 66 are powered from the Vdda level of the first power supply domain. The level shifter circuit 54 and frequency divider circuit 56 are powered from the Vddb level of the second power supply domain. A further level shifting circuit 58 receives the oscillating feedback signal 15 Ffb and the oscillating reference signal 17 Fref and functions to level shift those oscillating signals from the Vddb level of the second power supply domain to the Vdda level of the first power supply domain. The level shifter circuit 54 functions to shift the oscillating output signal 13 Fout from the Vs voltage level to the Vddb level of the second power supply domain.
A power management circuit 80 is provided to generate the voltages of the two different power supply domains. From an input supply voltage Vsupply provided, for example, by an off-chip power supply, a reference voltage generator circuit 82, for example, a bandgap reference voltage generator circuit, is used to generate a reference voltage Vref (that may comprise the bandgap voltage Vbg). A first voltage regulator, for example, a low drop out (LDO) type linear voltage regulator 84, generates the Vdda level positive voltage for the first power supply domain from the supply voltage Vsupply and the reference voltage Vref, where Vref is reference voltage for the error amplifier of the regulator. A second voltage regulator, for example, a high drop out (HDO) type linear voltage regulator 86, generates the Vddb level positive voltage for the second power supply domain from the supply voltage Vsupply and the reference voltage Vref, where Vref is the reference voltage for the error amplifier of the regulator. The ground voltages for the first and second power supply domains may be shared in common or be separate. FIG. 4 shows a basic circuit diagram of a conventional a linear regulator circuit of the type used for the voltage regulators 84 and 86 with error amplifier 70 and power transistor 72 powered from the input supply voltage Vsupply and with an input of the error amplifier coupled to receive the reference voltage Vref. The voltage level of the regulated output voltage Vdda or Vddb is set by the resistive divider 74 in the feedback loop for the error amplifier.
Because of the relatively high oscillation frequency fo of the oscillating output signal fout and the large power consumption needed to generate the signal, the level shifter circuit 54 which functions to shift the frequency signal Fout to the Vddb level second power supply domain must be designed for high speed and high power operation. Thus, the level shifter circuit 54 is a significant consumer of current within the frequency synthesizer circuit 50. As the frequency synthesizer circuit 50 may be a component of a device powered by a battery, there is a need in the art address and reduce current consumption. There is an additional challenge in that the digital circuits, such as the level shifter circuit 54, must meet a certain maximum speed requirement even at a lowest possible supply voltage in the slow process corner and the worst case temperature value.